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Patent # Description
US-7,548,097 Flyback current control
One embodiment of the invention includes a power driver system. The power driver system comprises a power transistor that is activated to provide power to a load...
US-7,547,630 Method for stacking semiconductor chips
In a semiconductor system (100) including a chip (101) and a workpiece (102), the chip has metal-filled vias (140) positioned between contact pads (120) and the...
US-7,547,596 Method of enhancing drive current in a transistor
A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective...
US-7,546,636 Authorization control circuit and method
An authorization control circuit (10) comprises a digital signal processor (12) operable to provide digital data output, determine an authorization state, and...
US-7,546,503 Selecting between tap/scan with instructions and lock out signal
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an...
US-7,546,502 1114.9 tap linking modules
IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for...
US-7,546,501 Selecting test circuitry from header signals on power lead
The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device....
US-7,546,437 Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses
A processor adapted to couple to external memory. The processor comprises a controller and data storage (e.g., cache memory). The data storage is configurable to...
US-7,546,392 Data transfer with single channel controller controlling plural transfer controllers
A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data...
US-7,546,391 Direct memory access channel controller with quick channels, event queue and active channel memory protection
A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals...
US-7,545,890 Method for upstream CATV coded modulation
The present invention provides an encoding method and a class of decoding methods that provide methods for high throughput and high robustness digital...
US-7,545,658 DC-DC boost converter with a charge pump
A DC-DC boost converter comprises a charge pump selectively operating in a voltage doubler or in a voltage tripler mode. A switching arrangement connects the...
US-7,545,316 Apparatus and methods to share time and frequency data between a host processor and a satellite positioning...
Methods and apparatus to share time and frequency data between a host processor and a satellite position system (SPS) receiver in a satellite positioning system...
US-7,543,285 Method and system of adaptive dynamic compiler resolution
A method and system of adaptive dynamic compiler resolution. At least some of the illustrative embodiments are a computer-implemented method comprising compiling...
US-7,543,205 Control signal synchronization of a scannable storage circuit
A system of control signal synchronization of a scannable storage circuit includes any number of storage circuits interconnected together with logic circuitry to...
US-7,543,158 Hybrid cryptographic accelerator and method of operation thereof
For use in a system-on-a-chip (SoC) having a secure execution environment (SEE) containing secure memory, a cryptographic accelerator, a method of performing...
US-7,543,014 Saturated arithmetic in a processing unit
In some embodiments a system comprises an overflow control bit, a programmable saturation control bit, a processing unit, and a saturation unit coupled to the...
US-7,541,946 Relaxation oscillator based keypad decoder
The keypad interface element of this invention uses a relaxation oscillator and a digital keypad processor having a counter/timer to decode specific keys. The RC...
US-7,541,884 Methods and apparatus for crystal oscillator drift estimation and compensation
In at least some disclosed embodiments, a method includes receiving a burst of data out of multiple bursts of data subject to long-term frequency drift and...
US-7,541,872 Startup circuit for subregulated amplifier
A multi-stage circuit has a first stage powered by the output voltage of a next stage. A current source within the first stage provides a tail current for a...
US-7,541,836 Binary boolean output on input with more than two states
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring...
US-7,541,275 Method for manufacturing an interconnect
The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an...
US-7,539,868 Run-time firmware authentication
A computing platform (10) protects system firmware (30) using a manufacturer certificate (36). The manufacturer certificate binds the system firmware (30) to the...
US-7,539,488 Over-the-air download (OAD) methods and apparatus for use in facilitating application programming in wireless...
In one illustrative example, a wireless network device of a low data rate wireless personal area network (WPAN) or the like includes a controller, memory for...
US-7,539,044 Memory device with capacitor and diode
One embodiment of the present invention relates to an integrated circuit that includes a memory cell. The memory cell includes a capacitor configured to store a...
US-7,538,673 Voltage regulation circuit for RFID systems
A voltage regulation circuit for an RFID circuit having a voltage limiter circuit including a current sensing element for sensing current through the voltage...
US-7,538,613 Systems and methods for common mode detection
Various systems and methods for common mode detection are disclosed. As one example, a common mode detection circuit including a differential input stage, a...
US-7,537,988 Differential offset spacer
A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a...
US-7,537,347 Method of combining dispersed light sources for projection display
A method and system for combining light emitted by dispersed light sources for use in a projection display or similar system. A plurality of elongated and...
US-7,536,597 Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality...
An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic...
US-7,536,566 System architecture for a power distribution network and method of operation
Digital and analog functionality are separated and optimized in an Ethernet port architecture to free port circuit space for additional desired functionality. A...
US-7,536,017 Cross-talk cancellation
Audio cross-talk cancellation by inverse HRTF matrix only for low frequencies; high frequencies rely upon the natural barrier of a listener's head. The low...
US-7,535,285 Band-gap voltage reference circuit
A reference circuit. Included are first and second reference circuit blocks, first and second controllable current sources connected to supply current through...
US-7,535,280 Apparatus and method for shifting a signal from a first reference level to a second reference level
An apparatus for shifting a received signal at a first reference level to an output signal at a second reference level; the received signal including...
US-7,535,210 Predictive duty ratio generating circuit and method for synchronous boost converters operating in PFM mode
A synchronous DC-to-DC converter includes an inductor coupled to receive an input voltage, a first transistor having a source coupled to a first reference...
US-7,535,123 Apparatus and method for selectively coupling system with a first power supply or a second power supply
An apparatus for selectively coupling a system with a first power supply or a second power supply includes: (a) a first switch for effecting a first coupling of...
US-7,535,104 Structure and method for bond pads of copper-metallized integrated circuits
A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The...
US-7,535,066 Gate structure and method
A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
US-7,534,676 Method of forming enhanced device via transverse stress
In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of...
US-7,534,668 Method of fabricating etch-stopped SOI back-gate contact
The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without...
US-7,534,655 Method of arranging dies in a wafer for easy inkless partial wafer process
In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle...
US-7,534,630 Method of improving power distribution in wirebond semiconductor packages
A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and...
US-7,533,250 Automatic operand load, modify and store
A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled...
US-7,533,203 Method and system for rapidly starting up an IEEE 1394 network
According to one embodiment of the invention, a network system for carrying control data between a controller and a device to be controlled is provided. The...
US-7,532,874 Offset balancer, method of balancing an offset and a wireless receiver employing the balancer and the method
The present invention provides an offset balancer for use with a differential mixer employing a wireless reception and an offset quantifier configured to...
US-7,532,679 Hybrid polar/cartesian digital modulator
A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all...
US-7,532,672 Codecs providing multiple bit streams
According to an aspect of the present invention two streams data encoding corresponding information contained in a multimedia signal are generated with one...
US-7,532,661 Additional hierarchical preamble for support of FDMA channel in a multi-band OFDM system
A wireless device 10, 12 that distinguishes between multiple piconets is provided. The wireless device 10, 12 includes a preamble component operable to provide a...
US-7,532,610 Structured adaptive frequency hopping
Embodiments of the invention reduces the computational complexity of adaptive frequency hopping mechanisms while mitigating the effects of interference....
US-7,532,565 Mapping data tones onto guard tones for a multi-band OFDM system
A device (104, 106, 108) is provided for wireless communication. The device (104, 106, 108) includes a transmitter (200) operable to transmit an orthogonal...
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