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Patent # Description
US-7,587,757 Surveillance implementation in managed VOP networks
A procedure for accomplishing surveillance within a managed VoP network when end-user encryption/decryption and NAT are in place. The procedure comprises first...
US-7,587,648 Integrated circuit having electrically isolatable test circuitry
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test....
US-7,587,644 Scan testing using response pattern as stimulus pattern after reset
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one...
US-7,587,642 System and method for performing concurrent mixed signal testing on a single processor
The present application describes a system and method for testing semiconductor devices and specifically for testing mixed signal semiconductor devices. The test...
US-7,587,583 Method and system for processing a "WIDE" opcode when it is not used as a prefix for an immediately following...
Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or...
US-7,587,577 Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch...
A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry...
US-7,587,539 Methods of inter-integrated circuit addressing and devices for performing the same
Inter-integrated circuit-capable devices for use on an inter-integrated circuit bus are disclosed. The inter-integrated circuit-capable devices include...
US-7,587,532 Full/selector output from one of plural flag generation count outputs
A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a "high water mark" to different levels for different...
US-7,587,525 Power control with standby, wait, idle, and wakeup signals
An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a...
US-7,587,315 Concealment of frame erasures and method
A decoder for code excited LP encoded frames with both adaptive and fixed codebooks; erased frame concealment uses repetitive excitation plus a smoothing of...
US-7,587,190 Systems and methods for low power clock generation
Various systems and methods for low power identification are described herein. For example, a radio frequency device including a radio frequency energy receiver....
US-7,586,993 Interleaver memory selectably receiving PN or counter chain read address
A method and apparatus for interleaving multiple frames of data as disclosed provide for an extremely streamlined approach to achieving both methods of...
US-7,586,668 Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...
US-7,586,659 Audio MEMS mirror feedback
A mirror device and a method for audio feedback of a MEMS mirror device are presented. The mirror device includes a mirror with a reflective surface located to...
US-7,586,376 Pre-power amplifier of load, switch array, and impedance compensation
A novel and useful load compensation circuit and associated pre-power amplifier constructed therefrom. The load compensation circuit functions to maintain a...
US-7,586,368 Simultaneous filtering and compensation circuitry and method in chopping amplifier
A chopper-stabilized amplifier (1B) having a first output (25) includes an input chopper (9) for chopping an input signal and applying it to the input of a first...
US-7,586,357 Systems for providing a constant resistance
A system for providing a desired substantially constant resistance includes a first transistor interconnected between a first node and a second node. The system...
US-7,586,349 CMOS integrated circuit for correction of duty cycle of clock signal
A CMOS integrated circuit (12) for correction of the duty cycle of a clock signal has a correction amplifier (16) to which a clock signal (14) is applied. The...
US-7,585,738 Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and...
A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative...
US-7,584,097 System and method for noisy automatic speech recognition employing joint compensation of additive and...
A system for, and method of, noisy automatic speech recognition employing joint compensation of additive and convolutive distortions and a digital signal...
US-7,583,976 Method and apparatus for transmit power control in wireless data communication systems
The distance between a first Multi Band Orthogonal Frequency Division Multiplex (MB-OFDM) data transceiver and a second or more such transceiver is determined...
US-7,583,764 Versatile system for interference tolerant packet detection in wireless communication systems
The present invention provides a system for obviating interference effects in packet detection within a wireless communications network. A plurality of reference...
US-7,583,594 Adaptive transmit window control mechanism for packet transport in a universal port or multi-channel environment
The transmit window size of a Simple Packet Relay Transport protocol packet transmission system can determine the efficiency of transmission and the memory...
US-7,583,156 Oscillator with multi-tap inductor, capacitors, and negative-Gm stages
System and method for increasing the frequency tuning range of a RF/microwave LC oscillator. An electronic communications device includes a controller to...
US-7,583,147 Buffer drive
The present invention relates to a CMOS buffer circuit for liquid crystal display (LCD) drivers, which includes a single stage operational transconductance...
US-7,583,133 Self-oscillating regulated low-ripple charge pump and method
Charge pump circuitry (30) compares bottom plate voltages of first (C1) and second (C2) flying capacitors in a current mode charge pump (1B) to a reference value...
US-7,582,963 Vertically integrated system-in-a-package
According to one embodiment of the invention, a method of forming a system-in-a-package includes providing a first substrate, coupling a first die to a top...
US-7,582,521 Dual metal gates for mugfet device
Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the...
US-7,581,159 Simplified decoding using structured and punctured LDPC codes
A communications transceiver for transmitting and receiving coded communications, with the coding corresponding to a low-density parity check code, is disclosed....
US-7,581,139 Distinguishing between two classes of trace information
A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time...
US-7,581,082 Software source transfer selects instruction word sizes
This invention employs a 16-bit instruction set that has a subset of the functionality of the 32-bit instruction set. In this invention 16-bit instructions and...
US-7,581,049 Bus controller
A single bus apparatus enables the simultaneous execution of both high-speed data transfer, which requires real time operation, and low-speed data transfer. At...
US-7,580,968 Processor with scaled sum-of-product instructions
A method of performing a scaled sum-of-product operation in a processor in response to multiply-and-accumulate (MAC) instructions. The method includes accessing...
US-7,580,967 Processor with maximum and minimum instructions
A method of operating a processor in a variable bit-length environment by performing a maximum limit function and minimum limit function. The method comprises...
US-7,580,965 Discrete-time convolution cycle reduction with programmable digital signal processor
A programming algorithm reduces from .theta. (2N.sup.2) to .theta. (N.sup.2) the number of multiply-and-accumulate (MAC) instructions required to perform a...
US-7,580,807 Test protocol manager for massive multi-site test
Disclosed herein is a massive multi-site (MMS) testing architecture. The MMS architecture includes a MMS interface on each of a plurality of devices under test....
US-7,580,768 Method of adjusting process variables in a processing flow
A method of adjusting process variables in a processing flow is disclosed. Processed samples are tested to determine sample parameters of the tested samples. The...
US-7,580,761 Fixed-size cross-correlation computation method for audio time scale modification
A time-domain time-scale modification method based on the synchronous overlap-and-add method consists of a generalization of the envelope-matching time-scale...
US-7,580,492 Clock recovery
Clock recovery apparatus having an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein the early/late voter...
US-7,579,975 DAC architecture for an ADC pipeline
A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one...
US-7,579,858 Semiconductor device and inspection method thereof
A semiconductor device is disclosed. The device has a photodiode isolated by element isolating regions (Ia, 14a, 14b) characterized by the following facts: on...
US-7,579,541 Automatic page sequencing and other feedback action based on analysis of audio performance data
Speech or musical performance is electronically analyzed using DSP techniques and is compared to a stored text script or musical score, to enable display of and...
US-7,578,422 Bond capillary design for ribbon wire bonding
A device (100) and method (200) for bonding a ribbon wire (104) to a workpiece (106) comprising feeding the ribbon wire through a passageway (116) of an...
US-7,577,981 Updating embedded firmware in a video system
An electronic device (18). The device comprises an analog (16) interface for receiving an analog waveform. The device also comprises an image screen (20) and...
US-7,577,774 Independent source read and destination write enhanced DMA
The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and...
US-7,577,565 Adaptive voice playout in VOP
Packetized CELP-encoded speech playout with frame truncation during silence and frame expansion method dependent upon voicing classification with voiced frame...
US-7,577,248 Method and apparatus for echo cancellation, digit filter adaptation, automatic gain control and echo...
Hands-free phones with voice activity detection using a comparison of frame power estimate with an adaptive frame noise power estimate, automatic gain control...
US-7,576,902 Spatial light modulator mirror metal having enhanced reflectivity
In accordance with the teachings of the present invention, a spatial light modulator mirror metal having enhanced reflectivity is provided. In a particular...
US-7,576,797 Automatic white balancing via illuminant scoring autoexposure by neural network mapping
Automatic white balancing and/or autoexposure as useful in a digital camera extracts color channel gains from comparisons of image colors with reference colors...
US-7,576,759 Parallel dithering contour mitigation
A method of producing an image. Image data word comprising image data bits for a portion of the image is received at a first frame rate. At least two threshold...
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