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Patent # Description
US-7,623,286 System and method for displaying images
System and method for enhancing image quality in a display system. A preferred embodiment comprises a variable light source capable of producing a light of...
US-7,623,055 Weight level generating method and device utilizing plural weights at different time rates
A weight level generator is provided. Weight level generator W has plural weight generators 5-1-5-j. At least one of said plural weight generators is used at at...
US-7,622,955 Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention...
An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An...
US-7,622,244 Method for contaminant removal
Method for removing contaminants from a surface during semiconductor fabrication. A preferred embodiment comprises developing a resist layer on a top surface of...
US-7,620,867 IP core design supporting user-added scan register option
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test...
US-7,620,675 Image and audio transform methods
Inverse discrete cosine transform (type-III DCT), used in video/image and audio coding, is implemented in the form of FFT to lower computational complexity.
US-7,619,947 Integrated circuit having a supply voltage controller capable of floating a variable supply voltage
An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to...
US-7,619,397 Soft-start circuit for power regulators
One embodiment of the present invention includes a system for providing a soft-start for a power regulator comprising a differential transistor pair that...
US-7,619,241 Variable capacitor single-electron transistor including a P-N junction gate electrode
The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a...
US-7,619,198 Imaging device and imaging device drive method
The problem of the invention is to improve S/N and provide a high-sensitivity imaging device. The CMOS image sensor includes multiple pixels arranged in a...
US-7,618,870 Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure...
US-7,617,440 Viterbi traceback initial state index initialization for partial cascade processing
This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations...
US-7,617,430 Local and global address compare with tap interface TDI/TDO lead
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,617,429 Automatable scan partitioning for low power using external control
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
US-7,615,966 Method and apparatus for managing energy in plural energy storage units
A system for managing energy stored in a plurality of series connected energy storage units has a plurality of energy storage unit controllers, each controller...
US-7,615,805 Versatile system for optimizing current gain in bipolar transistor structures
Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and...
US-7,615,458 Activation of CMOS source/drain extensions by ultra-high temperature anneals
A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over...
US-7,615,425 Open source/drain junction field effect transistor
The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET)...
US-7,615,386 Thick oxide film for wafer backside prior to metalization loop
A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick...
US-7,613,970 TAP domain selection circuit with AUXI/O1 or TDI lead
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,613,951 Scaled time trace
The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is...
US-7,613,924 Encrypted and other keys in public and private battery memories
Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In...
US-7,613,905 Partial register forwarding for CPUs with unequal delay functional units
A data processing apparatus includes a register file and a plurality of functional units. At least one and not all the plurality of the functional units is a...
US-7,613,259 Mobile receiver phase correction circuit
A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (r.sub.j(i+.tau..sub.j), i=0-N-1) during a first...
US-7,612,612 Calibration circuitry and delay cells in rectilinear RF power amplifier
Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high...
US-7,612,584 Simultaneous LVDS I/O signaling method and apparatus
First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an...
US-7,612,454 Semiconductor device with improved contact fuse
One aspect of the invention provides an integrated circuit(IC) [400b]. The IC comprises transistors [410b] and contact fuses [422b]. The contact fuses each...
US-7,612,440 Package for an integrated circuit
According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of...
US-7,612,437 Thermally enhanced single inline package (SIP)
In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A...
US-7,612,422 Structure for dual work function metal gate electrodes by control of interface dipoles
Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or...
US-7,611,981 Optimized circuit design layout for high performance ball grid array packages
A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a...
US-7,611,943 Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation
A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116)....
US-7,611,939 Semiconductor device manufactured using a laminated stress layer
There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a...
US-7,611,247 Illumination aperture for projection display
An optical system and method of increasing the contrast of a projected image. The optical system (1800) comprises a combination of aperture stops (1810, 1812) in...
US-7,610,536 Select and enable leads connecting IC taps and embedded controller
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-7,610,518 Program counter range comparator with equality, greater than, less than and non-equal detection modes
An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators...
US-7,609,612 Multi-carrier transmitter for ultra-wideband (UWB) systems
System and method for a multi-carrier ultra-wideband (UWB) transmitter. A preferred embodiment comprises an UWB transmitter (for example, transmitter 300) taking...
US-7,609,277 Method and apparatus for spatial and temporal dithering
An apparatus and method for spatially and temporally dithering pixels. A pixel comprising at least one color component of a first size is provided. A dither...
US-7,608,916 Aluminum leadframes for semiconductor QFN/SON devices
A post-mold plated semiconductor device has an aluminum leadframe (105) with a structure including a chip mount pad and a plurality of lead segments without...
US-7,608,484 Non-pull back pad package with an additional solder standoff
Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback...
US-7,607,058 Removable and replaceable tap domain selection circuitry
Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is...
US-7,607,047 Method and system of identifying overlays
A method and system of identifying overlays. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system...
US-7,606,999 Merging branch information with sync points
A method for merging branch information with sync points is disclosed herein. The method comprises determining whether a sync point is to be generated concurrent...
US-7,606,991 Dynamic clock switch mechanism for memories to improve performance
This invention improves cache operation by dynamically extending one state of a clock signal supplied to a cache on operation cycles when a cache fill operation...
US-7,606,977 Context save and restore with a stack-based memory structure
A multi-threaded processor adapted to couple to external memory comprises a controller and data storage operated by the controller. The data storage comprises a...
US-7,606,703 Layered celp system and method with varying perceptual filter or short-term postfilter strengths
Layered code-excited linear prediction (CELP) speech encoders have progressively weaker perceptual weighting filters for each of the successive enhancement...
US-7,606,696 Programmable extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least...
US-7,606,164 Process of increasing source rate on acceptable side of threshold
A process (111,101) of sending packets of real-time information at a sender (311) includes initially generating packets of real-time information with a source...
US-7,605,845 Motion stabilization
Stabilization for devices such as hand-held camcorders segments a low-resolution frame into a region of reliable estimation, refines the motion vectors of that...
US-7,605,737 Data encoding in a clocked data interface
One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over...
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