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Patent # Description
US-7,551,701 Frequency domain training of prefilters with interference suppression
Prefilters for a receiver with multiple input branches are trained in the frequency domain. The frequency response B of a conditioned channel is determined...
US-7,551,413 Transient triggered protection of IC components
One embodiment provides a system for protecting at least one component in an integrated circuit (IC). The system includes a disconnect element that is...
US-7,551,114 Reducing power consumption in the early stages of a pipeline sub-ADC used in a time-interleaved ADC
A stage of a pipelined ADC used as a sub-ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a...
US-7,550,993 Glitch reduced compensated circuits and methods for using such
Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver...
US-7,550,980 System and method for characterizing a load at the end of a cable
Apparatus within power sourcing equipment and a method for determining whether a load within a powered device coupled to the power sourcing equipment via a cable...
US-7,550,856 Grooved substrates for uniform underfilling solder ball assembled electronic devices
A semiconductor assembly (300) comprising a semiconductor device (301), which has a plurality of metallic contact pads (302) and an outline by sides (303). A...
US-7,550,852 Composite metal column for mounting semiconductor device
An integrated circuit chip which has a plurality of pads and non-reflowable contact members to be connected by reflow attachment to external parts. Each of these...
US-7,550,343 Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth...
In one embodiment, a semiconductor structure used in manufacturing a semiconductor device includes a substrate layer. The structure also includes first and...
US-7,550,314 Patterned plasma treatment to improve distribution of underfill material
A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the...
US-7,550,046 Vapor deposition system using benzotriazole (BTA) and isopropyl alcohol for protecting copper interconnects
A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized...
US-7,549,071 Method for providing real-time power conservation in a processor
A method for providing power conservation in a processor in which, depending on the respective embodiment, a relative amount of idle time, activity time, or idle...
US-7,549,007 Portable computer having an interface for direct connection to a mobile telephone
The present invention provides a solution to the dual problems of mobility and portability associated with using a portable telephone in combination with a...
US-7,548,365 Semiconductor device and method comprising a high voltage reset driver and an isolated memory array
A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device...
US-7,548,179 MASH sigma delta modulator
A Multi-stage noise shaping Sigma Delta Modulator (MSDM) and method of processing data using the MSDM are disclosed. The MSDM is capable of operating at high...
US-7,548,097 Flyback current control
One embodiment of the invention includes a power driver system. The power driver system comprises a power transistor that is activated to provide power to a load...
US-7,547,630 Method for stacking semiconductor chips
In a semiconductor system (100) including a chip (101) and a workpiece (102), the chip has metal-filled vias (140) positioned between contact pads (120) and the...
US-7,547,596 Method of enhancing drive current in a transistor
A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective...
US-7,546,636 Authorization control circuit and method
An authorization control circuit (10) comprises a digital signal processor (12) operable to provide digital data output, determine an authorization state, and...
US-7,546,503 Selecting between tap/scan with instructions and lock out signal
A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an...
US-7,546,502 1114.9 tap linking modules
IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for...
US-7,546,501 Selecting test circuitry from header signals on power lead
The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device....
US-7,546,437 Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses
A processor adapted to couple to external memory. The processor comprises a controller and data storage (e.g., cache memory). The data storage is configurable to...
US-7,546,392 Data transfer with single channel controller controlling plural transfer controllers
A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data...
US-7,546,391 Direct memory access channel controller with quick channels, event queue and active channel memory protection
A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals...
US-7,545,890 Method for upstream CATV coded modulation
The present invention provides an encoding method and a class of decoding methods that provide methods for high throughput and high robustness digital...
US-7,545,658 DC-DC boost converter with a charge pump
A DC-DC boost converter comprises a charge pump selectively operating in a voltage doubler or in a voltage tripler mode. A switching arrangement connects the...
US-7,545,316 Apparatus and methods to share time and frequency data between a host processor and a satellite positioning...
Methods and apparatus to share time and frequency data between a host processor and a satellite position system (SPS) receiver in a satellite positioning system...
US-7,543,285 Method and system of adaptive dynamic compiler resolution
A method and system of adaptive dynamic compiler resolution. At least some of the illustrative embodiments are a computer-implemented method comprising compiling...
US-7,543,205 Control signal synchronization of a scannable storage circuit
A system of control signal synchronization of a scannable storage circuit includes any number of storage circuits interconnected together with logic circuitry to...
US-7,543,158 Hybrid cryptographic accelerator and method of operation thereof
For use in a system-on-a-chip (SoC) having a secure execution environment (SEE) containing secure memory, a cryptographic accelerator, a method of performing...
US-7,543,014 Saturated arithmetic in a processing unit
In some embodiments a system comprises an overflow control bit, a programmable saturation control bit, a processing unit, and a saturation unit coupled to the...
US-7,541,946 Relaxation oscillator based keypad decoder
The keypad interface element of this invention uses a relaxation oscillator and a digital keypad processor having a counter/timer to decode specific keys. The RC...
US-7,541,884 Methods and apparatus for crystal oscillator drift estimation and compensation
In at least some disclosed embodiments, a method includes receiving a burst of data out of multiple bursts of data subject to long-term frequency drift and...
US-7,541,872 Startup circuit for subregulated amplifier
A multi-stage circuit has a first stage powered by the output voltage of a next stage. A current source within the first stage provides a tail current for a...
US-7,541,836 Binary boolean output on input with more than two states
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring...
US-7,541,275 Method for manufacturing an interconnect
The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an...
US-7,539,868 Run-time firmware authentication
A computing platform (10) protects system firmware (30) using a manufacturer certificate (36). The manufacturer certificate binds the system firmware (30) to the...
US-7,539,488 Over-the-air download (OAD) methods and apparatus for use in facilitating application programming in wireless...
In one illustrative example, a wireless network device of a low data rate wireless personal area network (WPAN) or the like includes a controller, memory for...
US-7,539,044 Memory device with capacitor and diode
One embodiment of the present invention relates to an integrated circuit that includes a memory cell. The memory cell includes a capacitor configured to store a...
US-7,538,673 Voltage regulation circuit for RFID systems
A voltage regulation circuit for an RFID circuit having a voltage limiter circuit including a current sensing element for sensing current through the voltage...
US-7,538,613 Systems and methods for common mode detection
Various systems and methods for common mode detection are disclosed. As one example, a common mode detection circuit including a differential input stage, a...
US-7,537,988 Differential offset spacer
A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a...
US-7,537,347 Method of combining dispersed light sources for projection display
A method and system for combining light emitted by dispersed light sources for use in a projection display or similar system. A plurality of elongated and...
US-7,536,597 Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality...
An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic...
US-7,536,566 System architecture for a power distribution network and method of operation
Digital and analog functionality are separated and optimized in an Ethernet port architecture to free port circuit space for additional desired functionality. A...
US-7,536,017 Cross-talk cancellation
Audio cross-talk cancellation by inverse HRTF matrix only for low frequencies; high frequencies rely upon the natural barrier of a listener's head. The low...
US-7,535,285 Band-gap voltage reference circuit
A reference circuit. Included are first and second reference circuit blocks, first and second controllable current sources connected to supply current through...
US-7,535,280 Apparatus and method for shifting a signal from a first reference level to a second reference level
An apparatus for shifting a received signal at a first reference level to an output signal at a second reference level; the received signal including...
US-7,535,210 Predictive duty ratio generating circuit and method for synchronous boost converters operating in PFM mode
A synchronous DC-to-DC converter includes an inductor coupled to receive an input voltage, a first transistor having a source coupled to a first reference...
US-7,535,123 Apparatus and method for selectively coupling system with a first power supply or a second power supply
An apparatus for selectively coupling a system with a first power supply or a second power supply includes: (a) a first switch for effecting a first coupling of...
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