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Patent # Description
US-7,532,120 RFID power from handset transmissions
A radio frequency identification (RFID) tag comprises a transceiver and a component coupled to the transceiver. The transceiver is adapted to wirelessly receive...
US-7,532,041 Systems and methods for hysteresis control in a comparator
Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with...
US-7,531,895 Integrated circuit package and method of manufacture thereof
An integrated circuit (IC) package that comprises a lead frame. The lead frame has a downset portion and leads. The downset portion has an exterior surface that...
US-7,531,893 Power semiconductor devices having integrated inductor
An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a...
US-7,531,464 Semiconductive device fabricated using a substantially disassociated chlorohydrocarbon
The invention provides a method of fabricating a semiconductive device. In one aspect, the method comprises heating a gas mixture [225] comprising ...
US-7,531,436 Highly conductive shallow junction formation
The invention relates to a method of forming a shallow junction. The method (100) comprises forming source/drain extension regions with a non-amorphizing tail...
US-7,531,432 Block-molded semiconductor device singulation methods and systems
The invention discloses methods and systems for singulation of block-molded arrays of semiconductor devices. Preferred embodiments include methods and associated...
US-7,531,415 Multilayered CMP stop for flat planarization
A three layer film (116/114/112), such as nitride/oxide/nitride for a CMP stop layer (110). A gap filling material (120) is polished, stopping on the first film...
US-7,531,400 Methods for fabricating MOS transistor gates with doped silicide
Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and...
US-7,531,398 Methods and devices employing metal layers in gates to introduce channel strain
A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a...
US-7,529,996 DDR input interface to IC test controller circuitry
A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The...
US-7,529,995 Second state machine active in first state machine SHIFT-DR state
Serial scanning circuitry is connectable to test access port controller for transferring serial data to and from functional circuitry. The test access port...
US-7,529,015 Hidden micromirror support structure
Methods and apparatus for use with a micromirror element includes a micromirror a micromirror having a substantially flat outer surface disposed outwardly from a...
US-7,528,928 Projector configuration
A transport stream with embedded projector configuration data 208 being carried along with the video for use in digital cinema projector setup. The embedded...
US-7,528,759 Pipelined analog-to-digital converter
One embodiment of the present invention includes a pipelined analog-to-digital converter (ADC) comprising a plurality of pipeline stages. At least one of the...
US-7,528,661 Low quiescent current output stage and method with improved output drive
Circuitry for increasing the maximum output current magnitude of a diamond buffer (Q57,58,74,75) having increased maximum output current provides a bias current...
US-7,528,072 Crystallographic preferential etch to define a recessed-region for epitaxial growth
A semiconductor device comprising a gate structure on a semiconductor substrate and a recessed-region in the semiconductor substrate. The recessed-region has a...
US-7,528,024 Dual work function metal gate integration in semiconductor devices
The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes...
US-7,526,695 BIST with generator, compactor, controller, adaptor, and separate scan paths
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106,and controller 110 remain the same as in the known...
US-7,526,254 Digital radio front end with minimized IF signal path
A digital down converter (DDC) can be provided in a digital radio receiver front end to produce baseband I and Q signals using mixing, decimating and narrow and...
US-7,525,394 Ultra low power CMOS oscillator for low frequency clock generation
An ultra low power relaxation CMOS oscillator for low frequency clock generation comprises a current source and a pair of capacitors that are alternatingly...
US-7,525,305 Core wrappers with input and output linking circuitry
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
US-7,524,777 Method for manufacturing an isolation structure using an energy beam treatment
The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include...
US-7,524,109 Systems and methods for resistance compensation in a temperature measurement circuit
Various systems and methods for temperature measurement are disclosed. For example, some embodiments of the present invention provide methods for temperature...
US-7,523,422 Method of fabricating an integrated circuit to improve soft error performance
The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error...
US-7,523,329 Apparatus for and method of reducing power consumption in a cable modem
A novel apparatus and method of reduced power consumption for battery backup operation of a communication device such as a cable modem. When the cable modem...
US-7,523,306 Simplified CCMP mode for a wireless local area network
A system and method for generating a message integrity code, MIC, for a MAC protocol data unit in a wireless local area network, WLAN, operating according to the...
US-7,522,677 Receiver with low power listen mode in a wireless local area network
A receiver for a wireless local area network, WLAN, having a low power listening mode of operation. The receiver includes two separate paths in the analog front...
US-7,522,674 Linearly independent preambles for MIMO channel estimation with backward compatibility
A device and a method of characterizing a communications channel. The method includes transmitting a first part of a packet preamble using two or more antennas...
US-7,522,630 Unified channel access for supporting quality of service (QoS) in a local area network
Contention communications often requires a station to wait an inordinate amount of time before the station is able to transmit its data successfully. In many...
US-7,522,398 Method and apparatus for overcurrent protection in DC-DC power converters
A controller and method for a switched-mode power converter adaptively provides overcurrent protection by detecting a current in the power converter exceeding a...
US-7,522,368 Differential voice coil motor control
A disk drive controller including a differential voice coil motor control function is disclosed. The differential voice coil motor control function includes an...
US-7,522,085 Pipelined analog to digital converter without input sample/hold
The first stage of a plurality of stages in a pipelined analog to digital converter couples its input analog signal to both a first and second sample and hold...
US-7,522,003 Constant margin CMOS biasing circuit
A biasing circuit is presented. The biasing circuit includes a primary biasing circuit, a replica circuit and an amplifier. The primary circuit provides a...
US-7,521,980 Process and temperature-independent voltage controlled attenuator and method
A circuit includes a first variable resistor having a resistance which is variable in response to a resistance control signal. A resistance control circuit...
US-7,521,338 Method for sawing semiconductor wafer
Semiconductor wafer sawing systems and methods are described in which a wafer may be secured in a sawing position having a surface exposed to incur sawing with...
US-7,521,291 Method for manufacturing a semiconductor device
The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing...
US-7,521,284 System and method for increased stand-off height in stud bumping process
System and method for creating single stud bumps having an increased stand-off height. A preferred embodiment includes a method of using a capillary for creating...
US-7,520,052 Method of manufacturing a semiconductor device
The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips...
US-7,519,955 Apparatus and method for transferring multiple scan length signal groups for JTAG boundary scans
In a JTAG test and debug environment, the signal groups for boundary scans can have several lengths including signal groups that are longer that the shift...
US-7,519,925 Integrated circuit with dynamically controlled voltage supply
An electronic system (10). The system comprises circuitry (P.sub.1) for receiving a system voltage from a voltage supply. The system also comprises circuitry...
US-7,519,884 TAM controller for plural test access mechanisms
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE...
US-7,519,532 Transcoding EVRC to G.729ab
Transcoding from EVRC to G.729ab with LSP parameters interpolated from EVRC to G.729ab, EVRC pitch used as input to G.729ab closed-loop pitch search, and G.729ab...
US-7,519,497 Apparatus and method for state selectable trace stream generation
A trace test and debug system for a target processor generates a program counter trace stream, a timing trace stream and a data trace stream. The target...
US-7,519,484 Power supply monitor
There is provided a power supply monitor circuit comprising a positive supply monitoring input, a negative supply monitoring input, and a voltage divider...
US-7,519,439 Efficient digital processor for feedback control applications
A digital processor (2, 102) for use in a digital controller (10) is disclosed. The digital processor (2, 102) includes a coefficient product memory (22) that...
US-7,519,387 Apparatus and method for wireless coupling of integrated circuit chips
In order to overcome the limitation of the integrated circuit chip inter-connectability resulting from the physical dimensions of the leads, a radio frequency...
US-7,519,333 Radio architecture for use with frequency division duplexed systems
A radio such as a frequency division duplex (FDD) radio (100) has a first local oscillator (LO.sub.1I and LO.sub.1Q) that is set to coincide with the transmitter...
US-7,519,135 Direct radio frequency (RF) sampling with recursive filtering method
A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating...
US-7,519,111 Apparatus and method for providing system and test clock signals to an integrated circuit on a single pin
In a configuration testing integrated circuits, the system clock signals are forced to the same frequency as the test clock signals. When the test clock signals...
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