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Patent # Description
US-7,541,884 Methods and apparatus for crystal oscillator drift estimation and compensation
In at least some disclosed embodiments, a method includes receiving a burst of data out of multiple bursts of data subject to long-term frequency drift and...
US-7,541,872 Startup circuit for subregulated amplifier
A multi-stage circuit has a first stage powered by the output voltage of a next stage. A current source within the first stage provides a tail current for a...
US-7,541,836 Binary boolean output on input with more than two states
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring...
US-7,541,275 Method for manufacturing an interconnect
The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an...
US-7,539,868 Run-time firmware authentication
A computing platform (10) protects system firmware (30) using a manufacturer certificate (36). The manufacturer certificate binds the system firmware (30) to the...
US-7,539,488 Over-the-air download (OAD) methods and apparatus for use in facilitating application programming in wireless...
In one illustrative example, a wireless network device of a low data rate wireless personal area network (WPAN) or the like includes a controller, memory for...
US-7,539,044 Memory device with capacitor and diode
One embodiment of the present invention relates to an integrated circuit that includes a memory cell. The memory cell includes a capacitor configured to store a...
US-7,538,673 Voltage regulation circuit for RFID systems
A voltage regulation circuit for an RFID circuit having a voltage limiter circuit including a current sensing element for sensing current through the voltage...
US-7,538,613 Systems and methods for common mode detection
Various systems and methods for common mode detection are disclosed. As one example, a common mode detection circuit including a differential input stage, a...
US-7,537,988 Differential offset spacer
A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a...
US-7,537,347 Method of combining dispersed light sources for projection display
A method and system for combining light emitted by dispersed light sources for use in a projection display or similar system. A plurality of elongated and...
US-7,536,597 Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality...
An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic...
US-7,536,566 System architecture for a power distribution network and method of operation
Digital and analog functionality are separated and optimized in an Ethernet port architecture to free port circuit space for additional desired functionality. A...
US-7,536,017 Cross-talk cancellation
Audio cross-talk cancellation by inverse HRTF matrix only for low frequencies; high frequencies rely upon the natural barrier of a listener's head. The low...
US-7,535,285 Band-gap voltage reference circuit
A reference circuit. Included are first and second reference circuit blocks, first and second controllable current sources connected to supply current through...
US-7,535,280 Apparatus and method for shifting a signal from a first reference level to a second reference level
An apparatus for shifting a received signal at a first reference level to an output signal at a second reference level; the received signal including...
US-7,535,210 Predictive duty ratio generating circuit and method for synchronous boost converters operating in PFM mode
A synchronous DC-to-DC converter includes an inductor coupled to receive an input voltage, a first transistor having a source coupled to a first reference...
US-7,535,123 Apparatus and method for selectively coupling system with a first power supply or a second power supply
An apparatus for selectively coupling a system with a first power supply or a second power supply includes: (a) a first switch for effecting a first coupling of...
US-7,535,104 Structure and method for bond pads of copper-metallized integrated circuits
A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The...
US-7,535,066 Gate structure and method
A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
US-7,534,676 Method of forming enhanced device via transverse stress
In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of...
US-7,534,668 Method of fabricating etch-stopped SOI back-gate contact
The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without...
US-7,534,655 Method of arranging dies in a wafer for easy inkless partial wafer process
In a method and system for fabricating a full wafer (600) having dies, an orientation marker (606), and a reference die (608), includes configuring a reticle...
US-7,534,630 Method of improving power distribution in wirebond semiconductor packages
A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and...
US-7,533,250 Automatic operand load, modify and store
A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled...
US-7,533,203 Method and system for rapidly starting up an IEEE 1394 network
According to one embodiment of the invention, a network system for carrying control data between a controller and a device to be controlled is provided. The...
US-7,532,874 Offset balancer, method of balancing an offset and a wireless receiver employing the balancer and the method
The present invention provides an offset balancer for use with a differential mixer employing a wireless reception and an offset quantifier configured to...
US-7,532,679 Hybrid polar/cartesian digital modulator
A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all...
US-7,532,672 Codecs providing multiple bit streams
According to an aspect of the present invention two streams data encoding corresponding information contained in a multimedia signal are generated with one...
US-7,532,661 Additional hierarchical preamble for support of FDMA channel in a multi-band OFDM system
A wireless device 10, 12 that distinguishes between multiple piconets is provided. The wireless device 10, 12 includes a preamble component operable to provide a...
US-7,532,610 Structured adaptive frequency hopping
Embodiments of the invention reduces the computational complexity of adaptive frequency hopping mechanisms while mitigating the effects of interference....
US-7,532,565 Mapping data tones onto guard tones for a multi-band OFDM system
A device (104, 106, 108) is provided for wireless communication. The device (104, 106, 108) includes a transmitter (200) operable to transmit an orthogonal...
US-7,532,259 Dynamic aperture for a light processing system
A method of processing light includes receiving an image to be displayed. The image has a brightness level. The method further includes generating light from a...
US-7,532,257 System and implementation for IF compensation for video decoders
Base band compensation for an IF stage in a television provides significant advantages over compensation applied to the composite signal. Each base band color...
US-7,532,120 RFID power from handset transmissions
A radio frequency identification (RFID) tag comprises a transceiver and a component coupled to the transceiver. The transceiver is adapted to wirelessly receive...
US-7,532,041 Systems and methods for hysteresis control in a comparator
Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with...
US-7,531,895 Integrated circuit package and method of manufacture thereof
An integrated circuit (IC) package that comprises a lead frame. The lead frame has a downset portion and leads. The downset portion has an exterior surface that...
US-7,531,893 Power semiconductor devices having integrated inductor
An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a...
US-7,531,464 Semiconductive device fabricated using a substantially disassociated chlorohydrocarbon
The invention provides a method of fabricating a semiconductive device. In one aspect, the method comprises heating a gas mixture [225] comprising ...
US-7,531,436 Highly conductive shallow junction formation
The invention relates to a method of forming a shallow junction. The method (100) comprises forming source/drain extension regions with a non-amorphizing tail...
US-7,531,432 Block-molded semiconductor device singulation methods and systems
The invention discloses methods and systems for singulation of block-molded arrays of semiconductor devices. Preferred embodiments include methods and associated...
US-7,531,415 Multilayered CMP stop for flat planarization
A three layer film (116/114/112), such as nitride/oxide/nitride for a CMP stop layer (110). A gap filling material (120) is polished, stopping on the first film...
US-7,531,400 Methods for fabricating MOS transistor gates with doped silicide
Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and...
US-7,531,398 Methods and devices employing metal layers in gates to introduce channel strain
A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a...
US-7,529,996 DDR input interface to IC test controller circuitry
A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The...
US-7,529,995 Second state machine active in first state machine SHIFT-DR state
Serial scanning circuitry is connectable to test access port controller for transferring serial data to and from functional circuitry. The test access port...
US-7,529,015 Hidden micromirror support structure
Methods and apparatus for use with a micromirror element includes a micromirror a micromirror having a substantially flat outer surface disposed outwardly from a...
US-7,528,928 Projector configuration
A transport stream with embedded projector configuration data 208 being carried along with the video for use in digital cinema projector setup. The embedded...
US-7,528,759 Pipelined analog-to-digital converter
One embodiment of the present invention includes a pipelined analog-to-digital converter (ADC) comprising a plurality of pipeline stages. At least one of the...
US-7,528,661 Low quiescent current output stage and method with improved output drive
Circuitry for increasing the maximum output current magnitude of a diamond buffer (Q57,58,74,75) having increased maximum output current provides a bias current...
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