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Patent # Description
US-7,567,883 Method and apparatus for synchronizing signals in a testing system
The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal...
US-7,567,624 System and method of communicating using combined signal parameter diversity
A system and method of data communication uses variable transmit antenna delays based on communication signal uplink measurements. The signals for each channel...
US-7,567,620 Data transmission scheme using channel group and DOCSIS implementation thereof
A novel apparatus for and a method of data transmission whereby an input data stream is distributed over a plurality of physical channels within a logical...
US-7,567,255 Color adjustment for clipped pixels
A control module for use in an image display system includes a gain module operable to amplify a signal received by the control module and to communicate an...
US-7,567,138 Single-electron injection/extraction device for a resonant tank circuit and method of operation thereof
A system for reducing phase-noise in a resonant tank circuit. The system includes a single-electron device configured to inject a single electron into the...
US-7,567,134 System and method for synchronizing multiple oscillators
A system and method for synchronizing an oscillator with multiple phases at a desired phase angle difference. A relative measure of a phase angle difference...
US-7,567,116 Voltage converting circuit and battery device
A voltage converting circuit and a battery device, aimed at the problem that the breakdown voltage required for the driving input of the selected switch element...
US-7,567,105 High speed controller area network receiver having improved EMI immunity
A CAN receiver architecture design that provides better immunity against EMI interference than conventional designs is disclosed herein. This CAN receiver...
US-7,566,652 Electrically inactive via for electromigration reliability improvement
A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second...
US-7,566,627 Air gap in integrated circuit inductor fabrication
In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of...
US-7,566,595 Method of making and using guardringed SCR ESD protection cell
Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an...
US-7,565,995 Roller wire brake for wire bonding machine
While fabricating a packaged semiconductor chip, a wire is bonded on a chip contact pad using a wire bonding machine. A bond head of the wire bonding machine is...
US-7,565,385 Embedded garbage collection
An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection...
US-7,565,125 Telecommunications receiver with automatic gain control
A receiver 30 has an adjustable gain control circuit 32 that provides gain control base on the magnitude of the signal at the input of an analog-to-digital...
US-7,565,111 Single-antenna interference cancellation receiver in time slot communication system
A receiver (MST) for use in a modulated communications system wherein data is communicated in a time-slotted format. The receiver comprises circuitry (22) for...
US-7,564,904 Apparatus for and method of detection of powered devices over a network
A novel mechanism for detecting the presence of powered devices over a network. A unique, infinite pseudo-random sequence of pulses are generated and transmitted...
US-7,564,868 Configuration DSL transceiver
A DSL modem (21) including a configurable digital transceiver (30) is disclosed. The digital transceiver (30) includes a configuration register (43), or other...
US-7,564,826 Apparatus for and method of synchronization and beaconing in a WLAN mesh network
A novel and useful synchronization mechanism that functions to provide a uniform time base for mesh points in a WLAN mesh based network. The invention enables...
US-7,564,725 SRAM bias for read and write
An integrated circuit includes a SRAM array including a plurality of SRAM cells arranged in a plurality of rows and columns and having a plurality of word lines...
US-7,564,391 Sigma delta modulator summing input, reference voltage, and feedback
A multibit sigma delta modulator for conveting an analog input signal (Vin) into a multibit digital output signal is disclosed. In one embodiment, the multibit...
US-7,564,389 Discrete-time, single-amplifier, second-order, delta-sigma analog-to-digital converter and method of operation...
A discrete-time, single-amplifier, second-order, delta-sigma analog-to-digital converter (DT-SADS ADC) and a method of operating the same. The DT-SADS ADC...
US-7,564,077 Performance and area scalable cell architecture technology
An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The...
US-7,563,168 Audio effect rendering based on graphic polygons
A method to supply audio effects to video games employs graphics information of sound source objects and sound interacting objects in a real time physical model...
US-7,562,360 Method and system for firmware downloads
A method and system for downloading firmware by a device controller from a data source while connected to a host. The device controller connects to the host and...
US-7,562,333 Method and process for generating an optical proximity correction model based on layout density
A method (300) for generating an optical proximity correction model for a mask layout having an asymmetric feature structure includes fabricating a mask (310)...
US-7,562,315 Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout
Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage...
US-7,562,259 Distributed depth trace receiver
Input processing limitations may be solved by placing multiple units in series, with each unit recording some portion of the incoming data. This requires the...
US-7,562,170 Programmable extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least...
US-7,562,108 High bandwidth high gain receiver equalizer
A receiver equalizer with a first equalizer unit having a basic equalizer stage and a negative impedance cell connected to the basic equalizer stage. Preferably...
US-7,561,618 Reconfigurable chip level equalizer architecture for multiple antenna systems
A system comprising a plurality of adaptive equalizers adapted to couple to a plurality of receive antennas, each of the antennas capable of receiving a...
US-7,561,596 Systems and methods for multiplexing and demultiplexing multiple data sources
The present disclosure describes systems and methods for multiplexing multiple data sources Some illustrative embodiments include a method for combining multiple...
US-7,561,458 Ferroelectric memory array for implementing a zero cancellation scheme to reduce plateline voltage in...
Memory devices are provided, having a ferroelectric memory array and a zero cancellation system with one or more zero cancellation circuits for coupling a...
US-7,561,433 Apparatus and method for a clip device for coupling a heat sink plate system with a burn-in board system
In a burn-in test configuration wherein a chip board having a plurality of semiconductor chips engages a heat sink board having a plurality of heat sinks. When...
US-7,560,973 Gate driver circuit for power transistor
A circuit arrangement with a gate driver circuit for a power transistor is disclosed which is suitable for low voltage applications, permitting a rail-to-rail...
US-7,560,972 Methods and apparatus to reduce propagation delay of circuits
Methods and apparatus to reduce propagation delay of circuits are disclosed. A disclosed apparatus to reduce propagation delay of a circuit comprises a level...
US-7,560,962 Generating an output signal with a frequency that is a non-integer fraction of an input signal
Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero...
US-7,560,808 Chip scale power LDMOS device
A semiconductor device includes at least one macro-cell device, the macro-cell device comprising a plurality of LDMOS devices. A first conductive layer is formed...
US-7,560,792 Reliable high voltage gate dielectric layers using a dual nitridation process
Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor...
US-7,560,779 Method for forming a mixed voltage circuit having complementary devices
A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a...
US-7,560,385 Etching systems and processing gas specie modulation
A method and system for etching a substrate control selectivity of the etch process by modulating the gas specie of the reactants. The gas specie selectively...
US-7,560,379 Semiconductive device fabricated using a raised layer to silicide the gate
In one aspect, the invention provides a method of fabricating a semiconductive device 200 that comprises forming a raised layer [510] adjacent a gate [340] and...
US-7,560,324 Drain extended MOS transistors and methods for making the same
Drain extended MOS transistors (52) and fabrication methods (100) therefor are presented, in which a voltage drop region (80) is provided in a well (82) of a...
US-7,559,155 Method and system for drying semiconductor wafers in a spin coating process
The invention provides methods and apparatus for drying the backside of semiconductor wafers in a spin-coating environment. Solvent is evaporatively dried from a...
US-7,558,987 Token-based trace system
A system comprising a target hardware comprising multiple processor cores and an application. The system also comprises a host computer coupled to the target...
US-7,558,984 Apparatus and method for test and debug of a processor/core having advanced power management
An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit...
US-7,558,545 Semiconductor device for a tuner and diversity receiver
A semiconductor device for a tuner generates a local oscillation signal inside or selects a local oscillation signal introduced from the outside, and controls...
US-7,557,992 Multi-mode color filter
A multi-mode color filter 400 having an inner hub region 402 used to mount the color filter 400 to a motor shaft. A first track 404 and a second track 406 of...
US-7,557,932 Characterization of micromirror array devices using interferometers
The invention provides a method and apparatus for evaluating the quality of microelectromechanical devices having deformable and deflectable members using...
US-7,557,789 Data-dependent, logic-level drive scheme for driving LCD panels
System and method for driving an LCD using a data-dependent, logic-level drive scheme. A preferred embodiment comprises determining a desired state of each pixel...
US-7,557,745 Apparatus and method for managing access to the analog-to-digital conversion results
In an analog-to-digital converter used to convert and store in buffer registers signals from a plurality of peripheral devices, a mode is provided wherein the...
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